[pvrusb2] question about managing HVR-1900 from an embedded host

[Mark Atherton]

   Hi All,
   I am working on a small, low power embedded digital TV project (see
   [1]http://www.idesignz.org/DigiLiteZL/DigiLiteZL.htm, and associated
   FPGA modulator
   [2]http://www.idesignz.org/DigiLiteZL_FPGA/DigiLiteZL-FPGA.htm). One of
   the next steps of the project is to hook a real-time MPEG2 video
   encoder up to the system, running at a suitably low rate (maybe 1 or
   2Mb/s total stream rate). The power budget for the system does not
   allow for a PC, hence the desire to use a small embedded system.
   An HVR-1900 MPEG encoder is at hand, but only composite video and audio
   inputs are required. This product appears to contain a Conexant CX23416
   MPEG2 audio/video encoder, a CX25840 PAL/NTSC video decoder, and a
   Cypress FX2, or FX2LP USB interface. The unit has misc stuff associated
   with RF tuner etc, hopefully these can be ignored.
   Moving on to signal flow: an external PAL video source will be plugged
   into the HVR-1900, the HVR-1900 will be plugged into a custom
   dsPIC33EP512MU810 board (which has a USB 1.1 host). The dsPIC has the
   job of initially loading required firmware into the HVR-1900 then
   selecting the required encode mode and translating the incoming real
   time MPEG Program Stream into Transport Stream. This data will then be
   transferred via a new parallel interface to the FPGA DVB-S modulator
   (USB is currently used).
   So far the PVR-1900 has been attached to Ubuntu Studio 10.x via a USB
   1.1 hub, and it has been confirmed that the whole chain can generate a
   1Mb/s PS using V4L. This was all rather easier than expected and worked
   pretty much off the bat, so well done.that team.
   Having spent some time playing with a Cypress FX2 (CY7C68013) USB
   interface dev kit, it appears that the FX2 can accept firmware over the
   USB port, and run from it's internal 8k (FX2) or 16k (FX2LP) RAM using
   vendor command 0xA0. A second stage boot loader (vend_ax) is required
   if external RAM is required. Some amount of cleverness involves the
   device re-enumerating itself from default VID / PID (0x04B4 / 0x8613)
   once code has been loaded, so that alternate drivers can take over the
   boot and control process. It also appears that DID is used to
   differentiate the FX2 (DID 0x000x) from the FX2LP (DID 0xA00x).
   So the next challenge is to completely understand all steps required to
   boot up a PVR-1900. From then, an understanding is required how to
   configure and use the booted device.
   At a guess, boot sequence is something like:
   1) PVR-1900 is plugged into the host (dsPIC)
   2) host registers and enumerates the FX2 device within the PVR-1900
   using VID 0x04B4, PID 0x8613
   3) host downloads FX2 firmware (or second stage loader vend_ax) using
   vendor command 0xA0
   4) host releases FX2 8051 from reset, new code re-enumerates using
   alternate VID / PID combination
   -- at this point, the FX2 8051 is running a boot loader that will allow
   code loading of CX25840 and CX23416 --
   5) host loads CX25840 firmware (possibly using two wire interface)
   6) host loads CX23416 firmware (not a clue)
   7) host commands CX25840 to select video standard and input source
   8) host commands CX23416 to select MPEG encode profile, bit rate etc.
   9) host commands CX23416 to start encoding
   10) host fetches buffers of MPEG video using BULK transfers over EP2 or
   EP6 (?)
   11) host translates PS to TS, sending output video to FPGA via parallel
   interface
   12) repeat from 10
   Notes:
   13) is BT565 is used as video path between CX25840 to CX23416, if not,
   then what ?
   14) looks like Linux uses v4l-pvrusb2-73xxx-01.fw (16,384 bytes) to
   load into FX2
   15) looks like Linux uses v4l-cx25840.fw (16,382 bytes) to load into
   CX25840
   16) looks like Linux uses v4l-cx2341x-enc.fw (376,836 bytes) to load
   into CX23416
   Any corrections, pointers to relevant web pages, or other help to start
   filling in the great voids of understanding will be most appreciated.
   Many thanks,
   Mark
   PS Phew !

References

   1. http://www.idesignz.org/DigiLiteZL/DigiLiteZL.htm
   2. http://www.idesignz.org/DigiLiteZL_FPGA/DigiLiteZL-FPGA.htm